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W19B320AT/B
6. FUNCTIONAL DESCRIPTION
6.1 Device Bus Operation
6.1.1
Word/Byte Configuration
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.
When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled
by #CE and #OE.
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active
and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
6.1.2
Reading Array Data
To read array data from the outputs, the #CE and #OE pins must be set to V IL . #CE is the power
control and used to select the device. #OE is the output control and gates array data to the output
pins. #WE should stay at V IH . The #BYTE pin determines the device outputs array data whether in
words or bytes.
The internal state machine is set for reading array data when device power-up, or after hardware
reset. This ensures that no excess modification of the memory content occurs during the power
transition. In this mode there is no command necessary to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the device
data outputs. Each bank remains enabled for read access until the command register contents are
changed.
6.1.3
Writing Commands/Command Sequences
In writhing a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive #WE and #CE to V IL , and #OE to V IH .
For program operations, the #BYTE pin determines the device accepts program data whether in bytes
or in words. Refer to “Word/Byte Configuration” for more information.
The Unlock Bypass mode of device is to facilitate a faster programming. When a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to
"Word/Byte Configuration” section for details on programming data to the device using both standard
and Unlock Bypass command sequences.
The erase operation can erase a sector, multiple sectors, even the entire device. The device address
space is divided into four banks: Bank 1and Bank 4 contains the boot/parameter sectors; while Bank 2
and Bank 3 contain the larger sectors of uniform size. The “bank address” is the address bits required
to solely select a bank; while the “sector address” is the address bits required to solely select a sector.
Publication Release Date: December 27, 2005
-7-
Revision A4
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功能描述:IC FLASH 32MBIT 70NS 48TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ